To achieve the higher density and smaller size of semiconductor devices, a flip chip packaging is mostly employed to package the semiconductor chips on a substrate. The flip chip packaging is a packaging method in which semiconductor bear chips having no packaging structure are packaged face down on a wiring pattern of the substrate.
Conventionally, a packaging structure has been proposed in which another semiconductor chip is stacked on one semiconductor chip that is mounted by flip chip packaging (or another semiconductor chip is arranged three-dimensionally on one semiconductor chip) to reduce the packaging area (patent documents 1 to 3).
In patent document 1, another semiconductor chip is stacked on one semiconductor chip, and a wire bonding is employed for the connection between the upper semiconductor chip of the stack and the wiring pattern of the substrate (patent document 1).
Also, in patent documents 2 and 3, a packaging structure has been disclosed in which to arrange three-dimensionally another semiconductor chip on the upper side of one semiconductor chip, a specific interchange substrate (interchange component) is arranged on the substrate, and the upper semiconductor chip is supported by this interchange substrate (interchange component).                Patent document 1: JP-A-11-260851        Patent document 2: JP-A-2002-170921        Patent document 3: JP-A-2002-270760        